AMC7836_15 Datasheet, PDF (76/87 Pages) Texas Instruments – AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports

AMC7836
SLAS986B – NOVEMBER 2014 – REVISED FEBRUARY 2015
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During the conversion, the input current per channel varies with the total update time which is determined by the
number and type of channels (NCH) and the conversion rate setting of the CONV-RATE bit in the ADC
configuration register (address 0x10).
NOTE
The source of the analog input voltage must be able to charge the input capacitance to a
12-bit settling level within the acquisition time.
8.2.2.2 DAC Output Range Selection
The AMC7836 device includes 16 DACs split into four groups, each with four DACs. All of the DACs in a given
group share the same output voltage range. The output range for each DAC group is independent and is
programmable to either –10 to 0 V, –5 to 0 V, 0 to 10 V or 0 to 5 V. The DAC output ranges are configured by
following the configuration settings listed in Table 1.
Each DAC includes an output buffer is capable of generating rail-to rail voltages. The Electrical
Characteristics—DAC Specifications table lists the maximum source and sink capability of this internal amplifier.
The graphs in the Application Curves section show the relationship of both stability and settling time with different
capacitive loading structures.
8.2.3 Application Curves
15
10nF, Rising Edge
10
200pF, Rising Edge
5
0
-5
-10
-15
0
5
10
15
20
25
Time (µs)
C001
Code 0x400 to 0xC00 to within ½ LSB
Figure 118. DAC Settling Time vs Load Capacitance
15
10nF, Falling Edge
10
200pF, Falling Edge
5
0
-5
-10
-15
0
5
10
15
20
25
Time (µs)
C001
Code 0xC00 to 0x400 to within ½ LSB
Figure 119. DAC Settling Time vs Load Capacitance
9 Power Supply Recommendations
The preferred (not required) pin order for applying power is IOV_DD, DV_DD and AV_DD, AV_CC and lastly AV_EE,
AV_SSB, AV_SSC, and AV_SSD.When power sequencing, ensure that all digital pins are not powered or in an active
state while the IOV_DD pin ramps. Proper sequencing of the digital pins can be accomplished by attaching 10-kΩ
pullup resistors to the IOV_DD pin, or pulldown resistors to the DGND pin. See the supply voltage ranges in the
Recommended Operating Conditions table.
In applications where a negative voltage is applied to AV_EE, AV_SSB, AV_SSC, and AV_SSD first, the user may notice
some small negative voltages at other supply pins, such as the AV_DD, DV_DD, and AV_CC pins. The negative
voltages at the supply pins may exceed the values listed in the Absolute Maximum Ratings table, but because
these voltages are created from intrinsic circuitry, the voltage levels are safe for operation. Although these
negative voltages are observed on the pins, the user must still adhere to the guidelines specified in the the
Absolute Maximum Ratings table and verify that the inputs are driven within the range specified in the table. The
user should also ensure that current is only applied when operating with voltages between the ranges listed in
the Absolute Maximum Ratings table.
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