AMC7836_15 Datasheet, PDF (55/87 Pages) Texas Instruments – AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports

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AMC7836
SLAS986B – NOVEMBER 2014 – REVISED FEBRUARY 2015
7.6.4.7 DAC Clear Enable 0 Register (address = 0x18) [reset = 0x00]
Figure 80. DAC Clear Enable 0 Register (R/W)
7
CLREN-B7
R/W-0
6
CLREN-B6
R/W-0
5
CLREN-B5
R/W-0
4
CLREN-B4
R/W-0
3
CLREN-A3
R/W-0
2
CLREN-A2
R/W-0
1
CLREN-A1
R/W-0
0
CLREN-A0
R/W-0
Table 28. DAC Clear Enable 0 Register Field Descriptions
Bit Field
7
CLREN-B7
6
CLREN-B6
5
CLREN-B5
4
CLREN-B4
3
CLREN-A3
2
CLREN-A2
1
CLREN-A1
0
CLREN-A0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Description
This register determines which DACs go into clear state when a
clear event is detected as configured in the DAC-CLEAR-
SOURCE registers.
If CLRENn = 1, DAC_n is forced into a clear state with a
clear event.
If CLRENn = 0, a clear event does not affect the state of
DAC_n.
7.6.4.8 DAC Clear Enable 1 Register (address = 0x19) [reset = 0x00]
7
CLREN-D15
R/W-0
6
CLREN-D14
R/W-0
Figure 81. DAC Clear Enable 1 Register (R/W)
5
CLREN-D13
R/W-0
4
CLREN-D12
R/W-0
3
CLREN-C11
R/W-0
2
CLREN-C10
R/W-0
1
CLREN-C9
R/W-0
0
CLREN-C8
R/W-0
Bit Field
7
CLREN-D15
6
CLREN-D14
5
CLREN-D13
4
CLREN-D12
3
CLREN-C11
2
CLREN-C10
1
CLREN-C9
0
CLREN-C8
Table 29. DAC Clear Enable 1 Register Field Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Description
This register determines which DACs go into clear state when a
clear event is detected as configured in the DAC-CLEAR-
SOURCE registers.
If CLRENn = 1, DAC_n is forced into a clear state with a
clear event.
If CLRENn = 0, a clear event does not affect the state of
DAC_n.
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