AMC7836_15 Datasheet, PDF (32/87 Pages) Texas Instruments – AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports

AMC7836
SLAS986B – NOVEMBER 2014 – REVISED FEBRUARY 2015
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7.3.2.3 ADC Synchronization
A trigger signal must occur for the ADC to enter and exit the IDLE state. The ADC trigger can be generated
either through software (ICONV bit in the ADC trigger register, 0xC0) or hardware (GPIO2/ADCTRIG, pin 9). To
use the GPIO2/ADCTRIG pin as an ADC trigger, the pin must be configured accordingly in the GPIO
configuration register (address 0x12). When the pin is configured as a trigger, a falling edge on it begins the
sampling and conversion of the ADC.
In auto mode the ADC and temperature data registers (0x20 through 0x4B) are accessed by first issuing an ADC
UPDATE command in the register update register (address 0x0F). The ADC UPDATE command ensures the
latest available data for each input channel can be accessed without the need for complex synchronization
schemes between the AMC7836 device and the host controller. A single ADC UPDATE command updates all
ADC and temperature data registers. Therefore issuing multiple UPDATE commands is not necessary when
reading more than one ADC data register.
NOTE
The ADC UPDATE command and accessing of the ADC and Temperature data registers
does not interfere with the conversion process which ensures continuous ADC operation.
In direct mode the ADC and temperature data registers (0x20 through 0x4B) should only be accessed while the
ADC is in the IDLE state (see Figure 53). Although the total update time can be easily calculated, the device
provides a data-available indicator signal to track the ADC status. Failure to satisfy the synchronization
requirements could lead to erroneous data reads.
The data-available indicator signal is output through the GPIO3/DAV pin and as a data-available flag that is
accessible through the serial interface (DAVF bit in the general status register, 0x72). The GPIO3/DAV pin must
be configured in the GPIO configuration register (address 0x12) as an interrupt. After a direct-mode conversion is
complete and the ADC returns to the IDLE state, the DAVF bit is immediately set to 1 and the DAV pin is active
(low) which indicates that new data is available. The pin and flag are cleared automatically when a new
conversion begins or one of the ADC data or temperature data registers is accessed.
a) Direct Mode, Software Trigger
Trigger
CS
Command
1^st internal
trigger
Read
Command
> 2 µs
Trigger
Command
2^nd internal
trigger
Read
Command
DAV
ADCTRIG
CS
First CONVERSION of the channels
specified in the ADC MUX Registers
Second CONVERSION of the channels
specified in the ADC MUX Registers
b) Direct Mode, Hardware Trigger
1^st trigger
> 2 µs
2^nd trigger
3^rd trigger
Read
Command
Read
Command
DAV
First CONVERSION of the channels
specified in the ADC MUX Registers
Second CONVERSION of the channels
specified in the ADC MUX Registers
Third CONVERSION of the channels
specified in the ADC MUX Registers
Figure 53. ADC Direct-Mode Trigger Synchronization
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