AMC7836_15 Datasheet, PDF (67/87 Pages) Texas Instruments – AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports

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AMC7836
SLAS986B – NOVEMBER 2014 – REVISED FEBRUARY 2015
7.6.13.2 DAC Clear 1 Register (address = 0xB1) [reset = 0x00]
7
CLR-D15
R/W-0
6
CLR-D14
R/W-0
Bit Field
7
CLR-D15
6
CLR-D14
5
CLR-D13
4
CLR-D12
3
CLR-C11
2
CLR-C10
1
CLR-C9
0
CLR-C8
Figure 109. DAC Clear 1 Register (R/W)
5
CLR-D13
R/W-0
4
CLR-D12
R/W-0
3
CLR-C11
R/W-0
2
CLR-C10
R/W-0
1
CLR-C9
R/W-0
0
CLR-C8
R/W-0
Table 58. DAC Clear 1 Register Field Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Description
This register uses software to force the DAC into a clear state.
If CLRn = 1, DAC_n is forced into a clear state.
If CLRn = 0, DAC_n is restored to normal operation.
7.6.13.3 Power-Down 0 Register (address = 0xB2) [reset = 0x00]
7
PDAC-B7
R/W-0
6
PDAC-B6
R/W-0
Figure 110. Power-Down 0 Register (R/W)
5
PDAC-B5
R/W-0
4
PDAC-B4
R/W-0
3
PDAC-A3
R/W-0
2
PDAC-A2
R/W-0
1
PDAC-A1
R/W-0
0
PDAC-A0
R/W-0
Bit Field
7
PDAC-B7
6
PDAC-B6
5
PDAC-B5
4
PDAC-B4
3
PDAC-A3
2
PDAC-A2
1
PDAC-A1
0
PDAC-A0
Table 59. Power-Down 0 Register Field Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Description
After power-on or reset, all bits in the power-down register are
cleared to 0, and all the components controlled by this register
are either powered-down or off. The power-down register allows
the host to manage the AMC7836 power dissipation. When not
required, any of the DACs can be put into clamp mode and the
ADC and internal reference into an inactive low-power mode to
reduce current drain from the supply. The bits in the power-down
register control this power-down function. Set the respective bit
to 1 to activate the corresponding function.
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