TMS320C6713 Datasheet, PDF (75/150 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I − DECEMBER 2001 − REVISED MAY 2004
PLL and PLL controller
The TMS320C6713/13B includes a PLL and a flexible PLL Controller peripheral consisting of a prescaler (D0)
and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different
parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other
peripherals). Figure 15 illustrates the PLL, the PLL controller, and the clock generator logic.
+3.3 V
EMI filter
C1 C2
10 µF 0.1 µF
PLLHV
For Use
in System
CLKMODE0
CLKIN
PLLREF
PLLOUT
1
Reserved
0
DIVIDER D0
/1, /2,
..., /32
PLL
ENA
x4 to x25 1
0
D1EN (PLLDIV1.[15])
PLLEN (PLL_CSR.[0])
DIVIDER D1^†
/1, /2,
..., /32
ENA
SYSCLK1
(DSP Core)
D0EN (PLLDIV0.[15])
CLKOUT3
OSCDIV1
/1, /2,
..., /32
ENA
OD1EN (OSCDIV1.[15])
ECLKIN
D2EN (PLLDIV2.[15])
AUXCLK
(Internal Clock Source
to McASP0 and McASP1)
D3EN (PLLDIV3.[15])
DIVIDER D2^†
/1, /2,
..., /32
ENA
SYSCLK2
(Peripherals)
DIVIDER D3
/1, /2,
..., /32
ENA
SYSCLK3
(EMIF Clock Input)
1 0 EKSRC Bit
(DEVCFG.[4])
C6713/13B DSPs
EMIF
ECLKOUT
† _{Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.}
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV_DD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 15. PLL and Clock Generator Logic
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