TMS320C6713 Datasheet, PDF (53/150 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I − DECEMBER 2001 − REVISED MAY 2004
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
IPD/
PYP
GDP
TYPE^†
IPU‡
DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)
CLKR1/AXR0[6]
36
M1
I/O/Z
IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
DX1/AXR0[5]
32
L2
I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
TOUT1/AXR0[4]
13
F1
I/O/Z IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP0/AXR0[3]
17
G2
I/O/Z
IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
TOUT0/AXR0[2]
18
G1
I/O/Z
IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
DX0/AXR0[1]
20
H2
I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
DR0/AXR0[0]
27
J1
I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
TIMER 1
TOUT1/AXR0[4]
13
F1
O
IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP1/AHCLKX0
12
F2
I
IPD
Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock
(I/O/Z).
TIMER0
TOUT0/AXR0[2]
18
G1
O
IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
TINP0/AXR0[3]
17
G2
I
IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1/SCL1
McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1
clock (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
8
E1
I
— McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
CLKR1/AXR0[6]
36
M1
I/O/Z
IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
CLKX1/AMUTE0
33
L3
I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
DR1/SDA1
37
M2
I
McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
—
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
DX1/AXR0[5]
32
L2
O/Z
IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
FSR1/AXR0[7]
38
M3
I/O/Z
IPD
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
FSX1
31
L1
I/O/Z IPD McBSP1 transmit frame sync
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ resistor}
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be used to pull a signal
to the opposite supply rail.]
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