TMS320C6713 Datasheet, PDF (1/150 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I − DECEMBER 2001 − REVISED MAY 2004
D Highest-Performance Floating-Point Digital
D 16-Bit Host-Port Interface (HPI)
Signal Processors (DSPs): C6713/C6713B
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 300-, 225-, 200-MHz (GDP), and 200-,
167-MHz (PYP) Clock Rates
− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
− 2400/1800, 1800 /1350 , 1600 /1200 , and
1336 /1000 MIPS /MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
D Advanced Very Long Instruction Word
D Two Multichannel Audio Serial Ports
(McASPs)
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
(VLIW) TMS320C67x DSP Core
− Support for Slot Size:
− Eight Independent Functional Units:
8, 12, 16, 20, 24, 28, 32 Bits
− Two ALUs (Fixed-Point)
− Data Formatter for Bit Manipulation
− Four ALUs (Floating- and Fixed-Point)
− Wide Variety of I2S and Similar Bit
− Two Multipliers (Floating- and
Stream Formats
Fixed-Point)
− Integrated Digital Audio Interface
− Load-Store Architecture With 32 32-Bit
Transmitter (DIT) Supports:
General-Purpose Registers
− S/PDIF, IEC60958-1, AES-3, CP-430
− Instruction Packing Reduces Code Size
Formats
− All Instructions Conditional
− Up to 16 transmit pins
D Instruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
D Two Inter-Integrated Circuit Bus (I²C Bus)
− Byte-Addressable (8-, 16-, 32-Bit Data)
Multi-Master and Slave Interfaces
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
D L1/L2 Memory Architecture
D Two Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
D Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
D Two 32-Bit General-Purpose Timers
D Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
D Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
D IEEE-1149.1 (JTAG^†)
Boundary-Scan-Compatible
D Package Options:
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
− 208-Pin PowerPAD Plastic (Low-Profile)
Quad Flatpack (PYP)
− 272-Ball, Ball Grid Array Package (GDP)
D 0.13-µm/6-Level Copper Metal Process
Memory Space
− CMOS Technology
D Enhanced Direct-Memory-Access (EDMA)
D 3.3-V I/Os, 1.2^‡-V Internal (GDP & PYP)
Controller (16 Independent Channels)
D 3.3-V I/Os, 1.4-V Internal (GDP) (300 MHz
only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I²C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
† _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
‡ _{These values are compatible with existing 1.26V designs.}
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright  2004, Texas Instruments Incorporated
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