TMS320C6713 Datasheet, PDF (46/150 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I − DECEMBER 2001 − REVISED MAY 2004
TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with
the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
SIGNAL
NAME
CLKIN
CLKOUT2/GP[2]
CLKOUT3
CLKMODE0
PLLHV
TMS
TDO
TDI
TCK
TRST
EMU5
EMU4
EMU3
EMU2
EMU1
EMU0
PIN NO.
PYP GDP
204
A3
82
Y12
184
D10
205
C4
202
C5
192
B7
187
A8
191
A7
193
A6
197
B6
—
B12
—
C11
—
B10
—
D3
185
B9
186
D9
TYPE^†
I
O/Z
O
I
A^§
I
O/Z
I
I
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Terminal Functions
IPD/
IPU‡
DESCRIPTION
CLOCK/PLL CONFIGURATION
IPD Clock Input
IPD
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z)
IPD Clock output programmable by OSCDIV1 register in the PLL controller.
Clock generator input clock source select
0 − Reserved, do not use.
IPU
1 – CLKIN square wave [default]
For proper device operation, this pin must be either left unconnected or
externally pulled up with a 1-kΩ resistor.
Analog power (3.3 V) for PLL (PLL Filter)
JTAG EMULATION
IPU JTAG test-port mode select
IPU JTAG test-port data out
IPU JTAG test-port data in
IPU JTAG test-port clock
IPD
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet.
IPU Emulation pin 5. Reserved for future use, leave unconnected.
IPU Emulation pin 4. Reserved for future use, leave unconnected.
IPU Emulation pin 3. Reserved for future use, leave unconnected.
IPU Emulation pin 2. Reserved for future use, leave unconnected.
Emulation [1:0] pins
• Select the device functional mode of operation
EMU[1:0]
Operation
00
Boundary Scan/Functional Mode (see Note)
01
Reserved
10
Reserved
11
Emulation/Functional Mode [default] (see the IEEE 1149.1
IPU
JTAG Compatibility Statement section of this data sheet)
The DSP can be placed in Functional mode when the EMU[1:0] pins are
configured for either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the
internal pulldown (IPD) on the TRST signal must not be opposed in order to
operate in Functional mode.
For the Boundary Scan mode drive EMU[1:0] and RESET pins low.
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ resistor}
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be used to pull a signal
to the opposite supply rail.]
§ _{A = Analog signal}
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