TMS320C6713 Datasheet, PDF (128/150 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I − DECEMBER 2001 − REVISED MAY 2004
INTER-INTEGRATED CIRCUITS (I2C) TIMING (CONTINUED)
switching characteristics for I2C timings^† (see Figure 52)
NO.
PARAMETER
PYPA−167
PYP−200
GDPA−200
GDP−225
GDP−300
STANDARD
MODE
FAST
MODE
MIN MAX
MIN MAX
16
t_c(SCL)
Cycle time, SCL
10
2.5
17 t_d(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7
0.6
18
t_d(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
0.6
19
t_w(SCLL)
Pulse duration, SCL low
4.7
1.3
20
t_w(SCLH)
Pulse duration, SCL high
4
0.6
21 t_d(SDAV-SDLH) Delay time, SDA valid to SCL high
250
22 t_v(SDLL-SDAV) Valid time, SDA valid after SCL low (For I²C bus devices)
0
100
0 0.9
23
t_w(SDAH)
Pulse duration, SDA high between STOP and START conditions 4.7
1.3
24
t_r(SDA)
25
t_r(SCL)
Rise time, SDA
Rise time, SCL
1000 20 + 0.1C_b† 300
1000 20 + 0.1C_b† 300
26
t_f(SDA)
27
t_f(SCL)
Fall time, SDA
Fall time, SCL
300 20 + 0.1C_b† 300
300 20 + 0.1C_b† 300
28 t_d(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
4
0.6
29 C_p
Capacitance for each I2C pin
10
10
† _{Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.}
UNIT
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
µs
pF
SDA
SCL
Stop
26
23
19
25
21
20
Start
16
18
27
18
22
17
Repeated
Start
Figure 52. I²C Transmit Timings
24
28
Stop
128
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