TMS320C82 Datasheet, PDF (74/147 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C82
DIGITAL SIGNAL PROCESSOR
SPRS048 — APRIL 1998
read cycles (continued)
State
CLKOUT
READY
EXCEPT-[1:0]
STATUS[1:0]
RL-
RCA[16:0]
RAS-
DSF
TRG-/CAS-
W-
CAS-/DQM[7:0]
AD[63:0]
DBEN-
DDIN-
ad1
ad2
rl1
rl2
col
col
col
col
ad1
ad
Col A
c1
Col B
Col C
c2
c1
c2
c1
Note 2
c2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
01
11
11
11
00
Row
Note 1
Col A
Col B
Col C
Address / ATC
A
B
C
↓
↓
↓
A
B
C
Low unless Peripheral Data Transfer
Notes:
1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles.
2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration.
Figure 61. 1 cycle/column EDO DRAM Read Cycle
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