TMS320C82 Datasheet, PDF (122/147 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C82
DIGITAL SIGNAL PROCESSOR
SPRS048 — APRIL 1998
SDRAM refresh cycle
The SDRAM refresh cycle is performed when the TC receives an SDRAM cycle timing input (/EXCEPT[1:0]
= 11) at the start of a refresh cycle. The /RAS and /TRG/CAS outputs are driven low for 1 cycle to strobe a
refresh command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The
‘C82 outputs a 16-bit pseudo-address (used for refresh bank decode) on RCA[16:1]. The pseudo-address is
decremented once for each refresh that is performed.
Notes:
State
ad1
ad2
ac1
ac2
rf1
rf2
rf3
ad1
ad
CLKOUT
READY
EXCEPT-[1:0]
3/2
11
STATUS[1:0]
RL-
01 (Row)
RCA[16:0]
RAS-
DSF
Refresh pseudo-address
Note 1&2
TRG-/CAS-
W-
CAS-/DQM[7:0]
AD[63:0]
DBEN-
Address / ATC
DDIN-
Command
REFR
1. A minimum of three cycles is required between the CLKOUT edges of a DCAB command and a subsequent ACTV command.
2. A minimum of seven cycles is required between the CLKOUT edges of a REFR command and a subsequent REFR or ACTV
command.
Figure 102. SDRAM Refresh
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