TMS320C82 Datasheet, PDF (18/147 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C82
DIGITAL SIGNAL PROCESSOR
SPRS048 — APRIL 1998
memory fault registers
The five read-only memory fault registers contain information about memory address exceptions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLTOP
(0x0010)
Dest
Reserved
K
SZ i d x R Reserved
B lock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLTTAG
(0x0011)
22-B it C ache Tag A ddress
PDPDPDPD
S ubblock 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLTADR
(0x0012)
Faulting Address A ccessed by Instruction
FLTDTH
(0x0013)
Faulting W rite M ost S ignificant D ata W ord
FLTDTL
(0x0014)
Faulting W rite Least S ignificant D ata W ord
Dest - destination register
K - kind of operation
00 - load
10 - store
01 - unsigned load 11 - cache flush/clean
SZ - size of data
00 - 8 bit 10 - 32 bit
01 - 16 bit 11 - 64 bit
i - MP icache fault
d - MP dcache fault
Figure 16. Memory Fault Registers
x - DEA fault
R - m odified return sequence
Block - faulting block num ber
P - subblock present
D - dirty bit set
cache registers
The ILRU and DLRU registers track least recently used information for the sixteen instruction cache and
sixteen data cache blocks. The ITAGxx registers contain block addresses and the present flags for each
subblock. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each subblock.
ILRU ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8}
(0x0300)
DLRU
mru nmru nlru
lru
mru nmru nlru
lru
mru nmru nlru
lru
(0x0500)
set 3
set 2
set 1
765432
mru nmru nlru
set 0
10
lru
ITAG0-15
(0x0200 -
0x020F)
22-bit Tag Address
PPPP
Subblock 3 2 1 0
DTAG0-15
(0x0400 -
0x040F)
22-bit Tag Address
Subblock
mru - most recently used block
nmru - next most recently used block
nlru - next least recently used block
lru - least recently used block
PDPDPDPD
3 2 10
P - subblock present
D - subblock dirty
mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set.
Figure 17. Cache Registers
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