TMS320C82 Datasheet, PDF (100/147 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320C82
DIGITAL SIGNAL PROCESSOR
SPRS048 — APRIL 1998
read cycles (continued)
State
CLKOUT
READY
EXCEPT-[1:0]
STATUS[1:0]
RL-
RCA[16:0]
RAS-
DSF
TRG-/CAS-
W-
CAS-/DQM[7:0]
AD[63:0]
DBEN-
DDIN-
ad1 ad2 rl1 col col col col col col col col col rto ad1 ad
Note 2
Col A c1 c2 c3
Col B
c1 c2 c3
Col C
c1 c2 c3
3/2.
3/2. 3/2. 3/2. 3/2. 3/2. 3/2. 3/2. 3/2. 3/2. 3/2. 3/2.
01
11
11
11
00
Row
Note 1
Col A
Col B
Col C
Address / ATC
A
↓
A
B
↓
B
Low unless Peripheral Data Transfer
C
↓
C
Notes:
1. No RAS- high time requirements apply to these cycles.
2. Additional turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration.
Figure 82. 3 cycle/column SRAM Read Cycle
100
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