TMS320VC5401 Datasheet, PDF (73/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)^†
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
t_{su(BDRV-BCKXH)}
t_{h(BCKXH-BDRV)}
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
14
2 − 12H
ns
6
5 + 12H
ns
t_{su(BFXL-BCKXH)}
Setup time, BFSX low before BCLKX high
12
ns
t_c(BCKX)
Cycle time, BCLKX
12H
32H
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
Table 5−29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)^†
PARAMETER
MASTER^‡
MIN MAX
SLAVE
UNIT
MIN
MAX
t_{h(BCKXL-BFXL)}
t_{d(BFXL-BCKXH)}
Hold time, BFSX low after BCLKX low^§
Delay time, BFSX low to BCLKX high^¶
C−5 C+6
ns
T − 7 T +5
ns
t_{d(BCKXL-BDXV)}
Delay time, BCLKX low to BDX valid
−4
8 6H +3 10H + 17 ns
t_{dis(BCKXL-BDXHZ)}
Disable time, BDX high impedance following last data bit from
BCLKX low
−4
6 6H +1 10H + 19 ns
t_d(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D − 4 D +6 4H − 4 8H + 19 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{T = BCLKX period = (1 + CLKGDV) * 2H}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
LSB
t_{su(BFXL-BCKXH)}
MSB
t_c(BCKX)
BFSX
t_{dis(BCKXL-BDXHZ)}
BDX
Bit 0
BDR
Bit 0
t_{h(BCKXL-BFXL)}
t_d(BFXL-BDXV)
t_{su(BDRV-BCKXH)}
t_{d(BFXL-BCKXH)}
Bit(n-1)
Bit(n-1)
t_{d(BCKXL-BDXV)}
(n-2)
(n-3)
t_{h(BCKXH-BDRV)}
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
December 2000 − Revised February 2004
SPRS153C
73