TMS320VC5401 Datasheet, PDF (27/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−6 and
described in Table 3−4.
15
8
Reserved
R/W-0
7
1
0
Reserved
SWSM
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
NO.
15−1
0
Table 3−4. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NAME
RESET
VALUE
FUNCTION
Reserved
0 These bits are reserved and are unaffected by writes.
SWSM
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.3.2 Programmable Bank-Switching
The programmable bank-switching logic of the 5401 is functionally equivalent to that of the 548/549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program
or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross
the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 3−7
shows the BSCR and its bits are described in Table 3−5.
15
12
11
10
8
BNKCMP
PS−DS
Reserved
R/W-1111
R/W-1
R-0
7
3
2
1
Reserved
HBH
BH
R-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−7. Bank-Switching Control Register (BSCR), MMR Address 0029h
0
EXIO
R/W-0
December 2000 − Revised February 2004
SPRS153C
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