TMS320VC5401 Datasheet, PDF (58/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5−13 and Table 5−14 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5−9, Figure 5−10, Figure 5−11, and Figure 5−12).
Table 5−13. Ready Timing Requirements for Externally Generated Wait States^†
MIN MAX UNIT
t_su(RDY)
Setup time, READY before CLKOUT low
8
ns
t_h(RDY)
t_v(RDY)MSTRB
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low^‡
0
ns
4H−6 ns
t_h(RDY)MSTRB
Hold time, READY after MSTRB low^‡
4H
ns
t_v(RDY)IOSTRB
Valid time, READY after IOSTRB low^‡
5H−6 ns
t_h(RDY)IOSTRB
Hold time, READY after IOSTRB low^‡
5H
ns
† _{The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using}
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ _{These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.}
Table 5−14. Ready Switching Characteristics for Externally Generated Wait States^†
PARAMETER
MIN MAX UNIT
t_d(MSCL)
Delay time, MSC low to CLKOUT low
−1
3 ns
t_d(MSCH)
Delay time, CLKOUT low to MSC high
−1
3 ns
† _{The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using}
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
CLKOUT
A[19:0]
READY
t_su(RDY)
t_h(RDY)
t_v(RDY)MSTRB
MSTRB
t_h(RDY)MSTRB
t_v(MSCL)
t_v(MSCH)
MSC
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during accesses to external data space.
Wait State
Generated
by READY
Figure 5−9. Memory Read With Externally Generated Wait States
58 SPRS153C
December 2000 − Revised February 2004