TMS320VC5401 Datasheet, PDF (32/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
The selection of the sample rate generator (SRG) clock input source is made by the combination of the
CLKSM and SCLKME bit values as shown in Table 3−6.
Table 3−6. Sample Rate Generator Clock Source Selection
SCLKME
CLKSM
SRG Clock Source
0
0
CLKS (not available as a pin on 5401)
0
1
CPU clock
1
0
BCLKR pin
1
1
BCLKX pin
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is
automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the
SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by
setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the
BCLKX pin because the BCLKR output is automatically disabled.
The McBSP supports independent selection of multiple channels for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In
using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.
3.6 Hardware Timer
The 5401 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is
decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.
3.7 Clock Generator
The clock generator provides clocks to the 5401 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source.
NOTE: All revisions of the 5401 can be operated with an external clock source, provided that the proper voltage levels
be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8 V power supply
(CV_DD), rather than the 3 V I/O supply (DV_DD). Refer to the recommended operating conditions section of this document
for the allowable voltage levels of the X2/CLKIN pin.
The reference clock input is then divided by two (DIV mode) to generate clocks for the 5401 device, or the
PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency
by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an
adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5401
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
• A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5401 to enable the internal oscillator.
• An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
32 SPRS153C
December 2000 − Revised February 2004