TMS320VC5401 Datasheet, PDF (52/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8 Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR.
Table 5−7 and Table 5−8 assume testing over recommended operating conditions with MSTRB = 0 and
H = 0.5t_c(CO) (see Figure 5−5).
Table 5−7. Memory Read Timing Requirements
t_a(A)M
Access time, read data access from address valid^†
t_a(MSTRBL)
Access time, read data access from MSTRB low
t_su(D)R
Setup time, read data before CLKOUT low
t_h(D)R
t_h(A-D)R
Hold time, read data after CLKOUT low
Hold time, read data after address invalid
t_h(D)MSTRBH Hold time, read data after MSTRB high
† _{Address, PS, and DS timings are all included in timings referenced as address.}
MIN MAX UNIT
2H−9 ns
2H−10 ns
8
ns
0
ns
2
ns
2
ns
Table 5−8. Memory Read Switching Characteristics
PARAMETER
t_d(CLKL-A)
t_d(CLKH-A)
Delay time, CLKOUT low to address valid^†‡
Delay time, CLKOUT high (transition) to address valid^†§
t_d(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
t_d(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
t_h(CLKL-A)R
Hold time, address valid after CLKOUT low^†‡
t_h(CLKH-A)R
Hold time, address valid after CLKOUT high^†§
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{In the case of a memory read preceded by a memory read}
§ _{In the case of a memory read preceded by a memory write}
MIN MAX UNIT
−4
5 ns
−4
5 ns
−3
5 ns
−3
5 ns
−4
5 ns
−4
5 ns
52 SPRS153C
December 2000 − Revised February 2004