TMS320VC5401 Datasheet, PDF (47/81 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.3 Electrical Characteristics
PARAMETER
V_OH High-level output voltage
TEST CONDITIONS
I_OH = MAX
MIN TYP^† MAX UNIT
2.3
V
V_OL Low-level output voltage
Input current for _{D[15:0], HD[7:0]}
I_IZ
outputs in high
impedance
All other inputs
X2/CLKIN^}
I_OL = MAX
Bus holders enabled, DV_DD = MAX,
V_I = V_SS to DV_DD
DV_DD = MAX, V_O = V_SS to DV_DD
−175
−10
−40
0.5 V
175
µA
10
40
I_I
Input current
TRST
HPIENA
TMS, TCK, TDI, HPI^w
With internal pulldown
With internal pulldown
With internal pullups,
HPIENA = 0
(V_I = V_SS
to DV_DD)
−10
−10
−300
300
300 _µA
10
I_DDC
I_DDP
I_DD
All other input-only pins
Supply current, core CPU
Supply current, pins
Supply current,
standby
IDLE2
IDLE3
CV_DD = 1.8 V, f_clock = 50 MHz^¶, T_C = 25°C^#
DV_DD = 3.3 V, f_clock = 50 MHz^¶, T_C = 25°C^||
PLL × 1 mode, 50 MHz input
Divide-by-two mode, CLKIN stopped
−10
10
22
mA
30
mA
2
mA
20
µA
C_i
Input capacitance
5
pF
C_o
Output capacitance
5
pF
† _{All values are typical unless otherwise specified.}
‡ _{All revisions of the 5401 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin. It}
should be noted that the X2/CLKIN pin is referenced to the device 1.8 V power supply (CV_DD), rather than the 3 V I/O supply (DV_DD). Refer to the
recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§ _{HPI input signals except for HPIENA.}
¶ _{Clock mode: PLL × 1 with external source}
# _{This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution from}
on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
|| _{This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex}
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320LC54x Power Dissipation Application Report (literature number SPRA164).
Tester Pin _VLoad
Electronics
I_OL
50 Ω
CT
Output
Under
Test
I_OH
Where:
I_OL
I_OH
V_Load
C_T
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
= 40 pF typical load circuit capacitance
Figure 5−1. 3.3-V Test Load Circuit
December 2000 − Revised February 2004
SPRS153C
47