TMS34020A Datasheet, PDF (7/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Terminal Functions (Continued)
NAME
VCC†
VSS†
EMU0 – EMU2
EMU3
GI
R1, R0
I/O
DESCRIPTION
POWER
I Nominal 5-volt power supply inputs. 9 pins.
I Electrical ground inputs. 17 pins.
EMULATION CONTROL
I Emulation pins 0 – 2.
O Emulation pin 3.
MULTIPROCESSOR INTERFACE
I Bus grant input. External bus artitration logic drives GI low to enable the TMS34020 to gain access to the
local-memory bus. The TMS34020 must release the bus if GI is high so that another device can access the bus.
O Bus request and control. These two signals indicate a request for use of the bus in a multiprocessor system; they
are decoded as shown below:
R1 R0
00
01
10
11
Bus Request Type
High-priority bus request
Bus-cycle termination
Low-priority bus request
No bus request pending
A high-priority bus request provides for VRAM serial-data-register transfer cycles (midline or blanked), DRAM
refresh (when 12 or more refresh cycles are pending), or a host-initiated access. The external arbitration logic should
grant the request as soon as possible by asserting GI low.
A low-priority bus request is used to provide for CPU-requested access and DRAM refresh (when less than 12
refresh cycles are pending).
Bus-cycle termination status is provided so that the arbitration logic can determine that the device currently
accessing the bus is completing an access and other devices can compete for the next bus cycle. A no bus request
pending status is output when the currently active device does not require the bus on subsequent cycles.
VIDEO INTERFACE
CBLNK / VBLNK O Composite blanking/vertical blanking. You can program this signal to select one of two blanking functions:
Composite blanking for blanking the display during both horizontal and vertical retrace periods in
composite-sync-video mode.
Vertical blanking for blanking the display during vertical retrace in separate-sync-video mode.
Immediately following reset, this signal is configured as a CBLNK output.
CSYNC / HBLNK I/O Composite sync/horizontal blanking. You can program this signal to select one of two functions.
Composite sync (either input or output as set by a control bit in the DPYCTL register) in composite-sync-video
mode:
Input: Extracts HSYNC and VSYNC from externally generated horizontal sync pulses.
Output: Generates active-low composite-sync pulses from either externally generated HSYNC and VSYNC
signals or signals generated by the TMS34020’s on-chip video timers.
Horizontal blank (output only) for blanking the display during horizontal retrace in separate-sync-video mode.
Immediately following reset, this signal is configured as a CSYNC input.
† _{For proper TMS34020 operation, all VCC and VSS pins must be connected externally.}
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