TMS34020A Datasheet, PDF (45/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

TMS34020, TMS34020A
GRAPHICS PROCESSORS
HA/HBS
HCS
HREAD
HWRITE
HRDY
DATA
(out)
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Prevoius Read
Local-Memory Host Read I/O Cycle
Valid
HOE
Q4 Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4 Q1
HDST
LAD
I/O Data
GI
CAMD
RCA
Row
Column
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
*See clock stretch, page 21.
R1
Figure 22. Host Read Cycle From TMS34020 I/O Registers
The host read of the TMS34020 I/O registers suppresses the generation of TR/QE and CAS so that data is read
from the TMS34020 rather than from memory. DDOUT is enabled so that data CAN flow through external buffers
on the LAD bus to the host data latches. The TMS34020 I/O registers may be accessed in any of the host access
modes (random/same, block, or read/modify/write).
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