TMS34020A Datasheet, PDF (18/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
status codes
Status codes are output on LAD0 – LAD3 at the time of the falling edge of ALTCH and may be used to determine
the type of cycle that is being initiated. The following table lists the codes and their respective meanings.
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
STATUS
Coprocessor Code
Emulator Operation
Host Cycle
DRAM Refresh
Video-generated DRAM Serial Register Transfer
CPU-generated VRAM Serial Register Transfer
Write Mask Load
Color Latch Load
Data Access
Cache Fill
Instruction Fetch
Interrupt Vector Fetch
Bus Locked Operation
Pixel Operation
Block Write
Reserved
TYPE
Other
(00XX)
VRAM
(01XX)
CPU
(1XXX)
dynamic bus sizing
The TMS34020 supports dynamic bus sizing between 16 and 32 bits on any local memory access. Any
port/memory that is only 16 bits wide must assert SIZE16 low during Q1 (to be valid at the start of Q2) of the
bus cycle accessing the even memory word (LAD4 = 0) corresponding to its address.The TMS34020 then
performs another memory access to the next 16-bit (odd) word in memory. The TMS34020 samples the SIZE16
pin at the start of Q2 in the second cycle (access to odd word address) to determine to which half of the LAD
bus the port or memory is aligned. If the port is on LAD0 – LAD15, the SIZE16 input should be low during the
second cycle access (odd word); otherwise, if the port is on LAD16 – LAD31, the SIZE16 input must be high at
this time. The TMS34020 always performs two memory cycles to access the 16-bit wide memories, even when
attempting only a 16-bit transfer.
The TMS34020 outputs the four CAS strobes and LAD bus initially aligned for a 32-bit bus. If the memory is 16
bits wide, the two most significant CAS strobes are swapped with the two least significant strobes when it
accesses the second word, and the halves of the LAD bus are also swapped; therefore, 16-bit memories need
to respond only to the two CAS strobes corresponding to the upper or lower 16 bits of the LAD bus to which they
are connected.
Note that devices connected to LAD0 – LAD15 transfer the least significant word during the first cycle and the
most significant word during the second cycle. Data accesses on LAD16 – LAD31 transfer the most significant
word first, then the least significant word.
The second memory cycle forced by the SIZE16 pin is performed as a page-mode access if PGMD was low
during the first access. A read-write cycle to 16-bit page-mode memory requires five bus cycles that occur as
address, read0, read1, write0, write1. If a 16-bit transfer is interrupted due to a bus fault, the restart causes the
entire access to be restarted.
For memory that supports page-mode accesses (PGMD low), SIZE16 is sampled during each access to
memory. If SIZE16 is high on the even-word access, then a 32-bit transfer occurs over LAD0 – LAD31. If SIZE16
is low on the even-word access (16-bit wide memory), then it is sampled again on the odd-word access to
determine to which half of the LAD bus the memory is connected (low for connection to LAD0 – LAD15 or high
for connection to LAD16 – LAD31).
18
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443