TMS34020A Datasheet, PDF (1/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

• Instruction Cycle Time
– 100 ns . . . TMS34020A-40
– 125 ns . . . TMS34020-32
– 125 ns . . . TMS34020A-32
• Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
• Second-Generation Graphics Processor
– Object Code Compatible With the
TMS34010
– Enhanced Instruction Set
– Optimized Graphics Instructions
– TMS34082 Graphics Floating-Point
Interface
• Pixel Processing, XY Addressing, and
Window Checking Built into the Instruction
Set
• Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and 6 Arithmetic
Pixel-Processing Options (Raster-Ops)
• 512-Byte LRU On-Chip Instruction Cache
• Optimized DRAM/VRAM Interface
– Page-Mode for Burst Memory Operations
up to 40 Megabytes per Second
– Dynamic Bus Sizing
(16-Bit and 32-Bit Transfers)
– Byte-Oriented CAS Strobes
• Flexible Host Processor Interface
– Supports Host Transfers at up to
20 Megabytes per Second
– Direct Access to All of the TMS34020
Address Space
– Implicit Addressing
– Prefetch for Enhanced Read Access
• Flexible Multiprocessor Interface
• Programmable CRT Control
– Composite Sync Mode
– Separate Sync Mode
– Synchronization to External Sync
• Direct Support for Special Features of
1M VRAMs
– Load Write Mask
– Load Color Mask
– Block Write
– Write Using the Write Mask
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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