TMS34020A Datasheet, PDF (10/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
memory corresponding to the current contents of the cache segment. Each cache segment is further partitioned
into eight subsegments of four long words (32 bits) each. Each subsegment has associated with it a present
(P) flag to indicate whether the subsegment contains valid data.
The cache is loaded only when an instruction requested by the execution section of the TMS34020 is not already
contained within the cache. A least-recently-used (LRU) algorithm determines which of the four segments of
the cache is overwritten with new data. For this purpose, an internal four-by-two LRU stack keeps track of cache
usage. Although the cache is loaded so as to always fill a subsegment completely, not all eight subsegments
within a segment are necessarily filled (this is dependent upon the instruction stream).
status register
The status register (ST) is a special-purpose 32-bit register dedicated to status codes set by the results of implicit
and explicit compare operations and parameters used to specify the length and behavior of fields 0 and 1.
In addition, during an interrupt, the IX bit in the ST placed on the stack provides indication that execution of an
interruptible instruction (PIXBLT, FILL or LINE) was halted to service the interrupt.
The single-step bit causes a TRAP to the single-step vector (located at address FFFF FBE0h) after the
execution of one instruction when the bit is set high. Normal program execution occurs when the bit is set low.
fields, bytes, words, long words, pixels, and pixel arrays
The TMS34020 outputs a 28-bit address on LAD4 – LAD31, which is valid at the falling edge of ALTCH. The most
significant 27 bits (LAD5 – LAD31) define a 32-bit long word of physical memory; logically, however, the
TMS34020 views memory data as fields addressable at the bit level. The least significant bit of the 28-bit address
(LAD4) is used to select the odd or even word when accessing 16-bit memories (indicated by SIZE16 asserted
low). Primitive data types supported by the TMS34020 include bytes, words, long words, pixels, two
independent fields of from 1 to 32 bits, and user-defined pixel arrays.
Words and long words, respectively, refer to 16- and 32-bit values that are aligned on 32-bit boundaries.
The two independent fields are referenced as field 0 and field 1. The attributes of these fields (field size and sign
extension within a register) are defined in the status register as FS0, FE0, FS1, and FE1. Fields 0 and 1 are
specified independently to be signed or unsigned and from 1 to 32 bits in length. Bytes are special 8-bit cases
of the field data type, while pixels are 1, 2, 4, 8, 16, or 32 bits in length. In general, fields (including bytes) can
start and terminate on arbitrary bit boundaries; however, pixels must pack evenly into 32-bit long words.
pixel operations
Pixel arrays are two-dimensional data types of user-defined width, length, pixel depth (number of bits per pixel),
and pitch (distance between rows). A pixel or pixel array can be accessed by means of either its memory address
or its XY coordinates. Transfers of individual pixels or pixel blocks are influenced by the pixel-processing,
transparency, window-checking, plane-masking, pixel-masking, or corner-adjustment operations selected. For
further information, see the TMS34020 User’s Guide, literature number SPVU019.
transparency
Transparency is a mechanism that allows surrounding pixels in an array to be specified as invisible. This is useful
for ensuring that only the object and not the rectangle surrounding it are written to the display. The TMS34020
provides four transparency modes:
• No transparency.
• Transparency on result equal zero.
• Transparency on source equal COLOR0.
• Transparency on destination equal COLOR0.
Refer to the TMS34020 User’s Guide for more information.
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