TMS34020A Datasheet, PDF (66/82 Pages) Texas Instruments – GRAPHICS PROCESSORS

TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
local bus timing: bus control inputs (see Figure 41)
NO.
PARAMETER
’34020-32
’34020A-32
MIN
MAX
’34020A-40
MIN
MAX
UNIT
57 td(CK2_↑-ALL) Delay time, ALTCH low after LCLK2↑
58 td(CK1_↓-ALH) Delay time, ALTCH high after LCLK1↓
59
td(CK1_↑-LAV)
Delay time, LAD0 – LAD31 address valid after
LCLK1↑
tQ + 15
tQ + 15
tQ + 22
tQ + 13.5 ns
tQ + 13.5 ns
tQ + 20 ns
60
Hold time, LAD0 – LAD31 address valid after
th(LAV-CK2L) _{LCLK2 low}
tQ – 15 + s
tQ – 12 + s
ns
61
td(CTNV-LAD)
Delay time, LAD0 – LAD31 driven after earlier
of DDIN↓ or CAS↑ or TR/QE↑
tQ – 5 + s ^†
tQ – 5 + s ^†
ns
Hold time, LAD0 – LAD31 read data valid after
62 th(LAV-CTV) earlier of DDIN low or RAS, CAS, or TR/QE
0
high
2
ns
63
td(CK2_↓-LAV)
Delay time, LAD0 – LAD31 data valid after
LCLK2↓ (write)
tQ + 22 + s
tQ + 20 + s ns
Hold time, LAD0 – LAD31 data valid after
64 th(CK2L-LAV) _{LCLK2 low (write)}
tQ – 15
tQ – 13.5
ns
65
td(CK1_↑-RCV)
Delay time, RCA0 – RCA12 row address valid
after LCLK1↑
tQ + 22
tQ + 20 ns
66
td(CK2_↓-RCV)
Delay time, RCA0 – RCA12 column address
valid after LCLK2↓
tQ + 22+ s
tQ + 20+ s ns
67
th(RCV-CK2L)
Hold time, RCA0 – RCA12 address valid after
LCLK2 low
tQ – 15
tQ – 12
ns
68 td(CK1_↑-DIH) Delay time, DDIN high after LCLK1↑
69 td(CK1_↓-DIL) Delay time, DDIN low after LCLK1↓
70 td(CK1_↑-DOL) Delay time, DDOUT low after LCLK1↑
71 td(CK1_↓-DOH) Delay time, DDOUT high after LCLK1↓
72 td(CK2_↓-DOL) Delay time, DDOUT low after LCLK2↓
73
tsu(LAV-AL_↓)
Setup time, LAD0 – LAD31 data valid before
ALTCH↓
tQ + 15
tQ + 15
tQ + 15
tQ + 15
tQ + 15 + s
tQ – 16
tQ + 13.5 ns
tQ + 13.5 ns
tQ + 13.5 ns
tQ + 13.5 ns
tQ + 13.5 + s ns
tQ – 13
ns
74
ten(DAV-DIH)
Enable time, data valid after DDIN high
(see Note 4)
2tQ – 20
2tQ – 17 ns
75
tdis(DAV-DIL)
Disable time, data high-impedance after DDIN
low (see Note 4)
tQ – 12 + s
tQ – 10 + s ns
e
th(REL-RCV)
Hold time, RAS valid low after column address
valid
3tQ – 22
3tQ – 12
ns
f
th(CEL-RCV)
Hold time, CAS valid low after column address
valid
3tQ – 22
3tQ – 12
ns
g
th(WEH-RCV)
Hold time, WE valid low after column address
valid
4tQ – 22 + s
4tQ – 18 + s
ns
h th(LAV-WEH) Hold time, LAD data valid after WE valid high
tQ – 15
tQ – 12
ns
† _{These values are derived from characterization data and are not tested.}
NOTE 4: DDIN is used to control LAD bus buffers between the TMS34020 and local memory. Parameter 74 references the time for these data
buffers to go from the high-impedance state to an active level. Parameter 75 references the time for the buffers to go from an active level
to the high-impedance state.
66
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