TLC32040M Datasheet, PDF (7/30 Pages) Texas Instruments – ANALOG INTERFACE CIRCUIT

TLC32040M
ANALOG INTERFACE CIRCUIT
AIC DR or DX word bit pattern
A/D or D/A MSB,
1st bit sent
1st bit sent of 2nd byte
A/D or D/A LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AIC DX data word format section
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d1 d0
COMMENTS
Primary DX serial communication protocol
← d15 (MSB) through d2 go to the D/A
converter register
→ ^{0 0 The TX and RX Counter As are loaded with the TA and}
RA register values. The TX and RX Counter Bs
areloaded with TB and RB register values.
← d15 (MSB) through d2 go to the D/A
converter register
→ ^{0 1 The TX and Counter As are loaded with the TA + TA’}
and RA + RA’ register values. The TX and RX Counter
Bs are loaded with the TB and RB register values.
NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D
conversion periods to be changed by the addition of TA’
and RA’ master clock cycles, in which TA’ and RA’ can
be positive or negative or zero. Please refer to Table 1.
AIC Responses to Improper Conditions.
← d15 (MSB) through d2 go to the D/A
converter register
→ ^{1 0 The TX and Counter As are loaded with the TA - TA’}
and RA - RA’ register values. The TX and RX Counter
Bs are loaded with the TB and RB register values.
NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D
conversion periods to be changed by the subtraction of
TA’ and RA’ Master Clock cycles, in which TA’ and RA
can be positive or negative or zero. Please refer to
Table 1. AIC Responses to Improper Conditions.
← d15 (MSB) through d2 go to the D/A
converter register
→ ^{1 1 The TX and Counter As are loaded with the TA and}
RA register values. The TX and RX Counter Bs are
loaded with the TB and RB register values. After a
delay of four shift-clock cycles, a secondary
transmission will immediately follow to program the
AIC to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (Primary Communications) to the AIC will initiate
Secondary Communications upon completion of the Primary Communications.
Upon completion of the Primary Communication, FSX will remain high for four shift-clock cycles and will then go low and initiate the
Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. in this manner, the
Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents the
Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from skipping a
DAC output. It is important to note that in the synchronous mode, FSR will not be asserted during Secondary Communications.
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