TLC32040M Datasheet, PDF (27/30 Pages) Texas Instruments – ANALOG INTERFACE CIRCUIT

TLC32040M
ANALOG INTERFACE CIRCUIT
CLKOUT
FSX
DX
TMS32020/C25 FSR
DR
CLKR
CLKX
APPLICATION INFORMATION
MSTR CLK
VCC+
FSX
REF
DX
ANLG GND
FSR
TLC32040/TLC32041
DR
/
SHIFT CLK
TLC32042
VCC _–
VDD
DGTL GND
C = 0.2 µF, Ceramic
C
BAT 42†
C
–5 V
5V
0.1 µF
5V
C
† _{Thomson Semiconductors}
Figure 16. AIC Interface to SMJ32020/C25 Showing Decoupling Capacitors and Schottky Diode^†
PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN – input set is used; however, the auxiliary
input set, AUX IN + and AUX IN –, can be used if a second input is required. Each input set can be operated in
either differential or single-ended modes, since sufficient common-mode range and rejection are provided. The
gain for the IN +, IN –, AUX IN +, and AUX IN – inputs can be programmed to be either 1, 2, or 4 (see Table 2).
Either input circuit can be selected via software control. It is important to note that a wide dynamic range is
assured by the differential internal analog architecture and by the separate analog and digital voltage supplies
and grounds.
A/D band-pass filter, A/D band-pass filter clocking, and A/D conversion timing
The A/D band-pass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock
frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.
The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that RX
Counter A can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master
clock input frequencies.
The A/D conversion rate is then attained by frequency dividing the 288-kHz band-pass switched-capacitor filter
clock with RX Counter B. Thus unwanted aliasing is prevented because the A/D conversion rate is an integral
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
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