TLC32040M Datasheet, PDF (5/30 Pages) Texas Instruments – ANALOG INTERFACE CIRCUIT

TLC32040M
ANALOG INTERFACE CIRCUIT
INTERNAL TIMING CONFIGURATION
Master Clock
5.184 MHZ (1)
10.368 MHZ (2)
Divide by 4
Shift Clock
1.296 MHz (1)
2.592 MHz (2)
XTAL
Osc
20.736 MHz (1)
41.472 MHz (2)
TMS320
DSP
Optional External Circuitry
for Full-Duplex Modems
Divide
by 135
153.6 kHz
Clock (1)
Commercial
External
Front-End
Full-Duplex
Split-Band
Filters
TA Register
(5 Bits)
TA’ Register
(6 Bits)
(2s Compl)
Adder /
Subtractor
(6 Bits)
d0, d1 = 0,0
d0, d1 = 1, 1‡
d0, d1 = 0,1
d0, d1 = 1,0‡
TX Counter A
[TA = 9 (1)]
[TA = 18 (2)]
(6 Bits)
576-kHz
Pulses
RA Register
(5 Bits)
RA’ Register
(6 Bits)
(2s Compl)
Adder /
Subtractor
(6 Bits)
Divide by 2
TB Register
(6 Bits)
Low-Pass
Switched
Cap Filter
CLK = 288 kHz
Square Wave
TX Counter B
TB = 40, 7.2 kHz
TB = 36, 8.0 kHz
TB = 30, 9.6 kHz
TB = 20, 14.4 kHz
TB = 15, 19.2 kHz
D/A
Conversion
Frequency
Divide by 2
RB Register
(6 Bits)
Band-Pass
Switched
Cap Filter
CLK = 288 kHz
Square Wave
d0, d1 = 0,0
d0, d1 =
1,1‡
d0, d1 = 0,1
d0, d1 = 1,0‡
RX Counter A
[TA = 9 (1)]
[TA = 18 (2)]
(6 Bits)
576-kHz
Pulses
RX Counter B
RB = 40, 7.2 kHz
RB = 36, 8.0 kHz
RB = 30, 9.6 kHz
RB = 20, 14.4 kHz
RB = 15, 19.2 kHz
A/D
Conversion
Frequency
SCF Clock Frequency = ^{Master Clock Frequency}
2 × Contents of Counter A
† _{Split-band filtering can alternatively be performed after the analog input function via software in the SMJ320.}
‡ _{These control bits are described in the AIC DX data word format section.}
NOTE: Frequency 1, 20.736 MHz is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech
and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as
submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal frequency,
aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.
Frequency 2, 41.472 MHz is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal
processors.
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