TLC32040M Datasheet, PDF (3/30 Pages) Texas Instruments – ANALOG INTERFACE CIRCUIT

TLC32040M
ANALOG INTERFACE CIRCUIT
Terminal Functions
PIN
NAME
NO.
ANLG GND 17, 18
AUX IN +
24
AUX IN –
23
DGTL GND
9
DR
5
DX
12
EODR
3
EODX
11
FSR
4
FSX
14
IN+
26
IN–
25
MSTR CLK
6
OUT+
22
OUT–
21
REF
8
RESET
2
I/O
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
I Noninverting auxiliary analog input stage. This input can be switched into the band-pass filter and A/D converter
path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs will replace the IN +
and IN – inputs. If the bit is a 0, the IN + and IN – inputs will be used (see the AIC DX data word format section).
I Inverting auxiliary analog input (see the above AUX IN + pin description).
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
O This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits
from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal.
I This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal.
O End of data receive.(See the WORD/BYTE pin description and the Serial Port TIming dIagram.) During the
word-mode timing, this signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have
been transmitted from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor
upon completion of serial communications. Also, this signal can be used to strobe and enable external
serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications
between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after
the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the second byte
has been transmitted. The TMS32011 or TMS320C17 can use this low-going signal to differentiate between the
two bytes as to which is first and which is second.
O End of data transmit. See WORD/BYTE description and Serial Port Timing diagram. During the word-mode timing,
this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control or register
information have been transmitted from the SMJ320 serial port to the AIC. This signal can be used to interrupt a
microprocessor upon the completion of serial communications. Also, this signal can be used to strobe and enable
external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate parallel data-bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal
goes low after the first byte has been transmitted from the SMJ320 serial port to the AIC and is kept low until the
second byte has been transmitted. The DSP can use this low-going signal to differentiate between the two bytes
as to which is first and which is second.
O Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description, FSR
is held low during bit transmission. When FSR goes low, the SMJ320 serial port will begin receiving bits from the
AIC via the DR pin of the AIC. The most significant DR bit will be present on DR before FSR goes low. (See Serial
Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after secondary communication.
O Frame sync transmit. When this terminal goes low, the SMJ320 serial port will begin transmitting bits to the AIC
via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description, FSX is
held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams).
I Noninverting input to analog input amplifier stage
I Inverting input to analog input amplifier stage
I The master clock signal is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples of
the master clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred
between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configuration).
O Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a single-ended configuration.
O Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT+.
I/O The internal voltage reference is brought out on this terminal. Also an external voltage reference can be applied
to this terminal.
I A reset function is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. This reset function
initiates serial communications between the AIC and DSP. The reset function will initialize all AIC registers
including the control register. After a negative-going pulse on RESET, the AIC registers will be initialized to provide
an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers,
TA’ and RA’, will be reset to 1. The control register bits will be reset as follows (see AIC DX data word format
section).
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial-port communication to occur between the AIC and the DSP.
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