THS8133 Datasheet, PDF (7/23 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

programming example (continued)
T0
T1
T2
T3
THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
T4
T5
T6
T7
T8
T9
T10
BLANK
First registered sample on GYr[9–0] after L->H
on BLANK is interpreted as Pb[9–0]
RPr[9–0]ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
BGPYb[[99––00]]^{ÎÎÎÎÎÎPbÎÎÎ(0) ÎÎÎÎÎÎY(0)ÎÎÎÎÎÎPr(ÎÎÎ0) ÎÎÎYÎÎÎ(2)ÎÎÎÎÎÎPb(ÎÎÎ4) ÎÎÎYÎÎÎ(4)ÎÎÎÎÎÎPr(ÎÎÎ4) ÎÎÎYÎÎÎ(6)ÎÎÎÎÎÎPb(ÎÎÎ8) ÎÎÎYÎÎÎ(8) ÎÎÎÎÎÎPr(8ÎÎÎ)}
data path latency = 9 CLK cycles
ARPr, AGY,
ABPb output
Pb(0)
corresponding
registered Y(0)
to Pr(0),
registered _Pr(0)
Y(0), Pb(0)
registered
Figure 5. Input Format and Latency YPbPr 4:2:2 1×10 Bit Mode
sync generation
Additional control inputs SYNC and SYNC_T enable the superposition of an additional current onto the AGY
channel or on all three channels, depending on the setting of INS3_INT. By combining the SYNC and SYNC_T
control inputs, either bi-level negative going pulses or tri-level pulses can be generated. Depending on the timing
controls for these signals, both horizontal and vertical sync signals can be generated. Assertion of SYNC (active
low) will identify the sync period, while assertion of SYNC_T (active high) within this period will identify the
positive excursion of a tri-level sync.
Refer to the application information section for practical examples on the use of these control inputs for sync
generation.
blanking generation
An additional control input BLANK is provided that will fix the output amplitude on all channels to the blanking
level, irrespective of the value on the data input ports. However, sync generation has precedence over blanking;
that is, if SYNC is low, the level of BLANK is don’t care. The absolute amplitude of the blanking level with respect
to active video is determined by the GBR or YPbPr operation mode of the device. Refer to the application
information section for practical examples on the use of this control input for blank generation.
Figure 6 shows how to control SYNC, SYNC_T, and BLANK signals to generate tri-level sync levels and blanking
at the DAC output. A bi-level (negative) sync is generated similarly by avoiding the positive transition on
SYNC_T during SYNC low.
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