THS8133 Datasheet, PDF (17/23 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
APPLICATION INFORMATION
SMPTE 274M (continued)
+300
Vertical
Sync
0
Blanking
–300
OH
+350
+300
Broad Pulse
P’B, P’r
0
–300
–350
+700
+300
Y’,R’,G’,B’
0
–300
OH
Figure 14. SMPTE 274M Analog Interface Horizontal Timing Details^†
† _{This figure is for illustration purposes only. Consult the latest SMPTE 274M standard when designing a compliant system.}
For GBR operation, Table 9 lists the THS8133 full-scale output currents that produce compliant signals to the
standard after proper termination. These amplitudes are valid also in YPbPr mode for the Y channel. For GBR
operation, the device needs to be configured with INS3_INT high, corresponding to the GBR with sync-on-all
operation mode of Table 1.
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