THS8133 Datasheet, PDF (11/23 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION

THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
electrical characteristics over recommended operating conditions with f_CLK = 80 MSPS and use
of internal reference voltage V_ref, with R_(FS) = R_(FSnom) (unless otherwise noted) (continued)
analog (DAC) outputs
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INL
DNL
PSRR
DAC resolution
Integral nonlinearity
Differential nonlinearity
Power supply ripple rejection ratio of DAC
output (full scale)
Static, best fit
Static
f = 100 kHz (see Note 4)
f = 1 MHz (see Note 4)
10
10
±0.6
–0.25/0.5
37
43
bits
±1.2 LSB
±1 LSB
dB
XTALK
Crosstalk between channels
f up to 30 MHz, (see Note 5)
–55 dB
VO(ref)
ro(VREF)
G(DAC)
Voltage reference output
VREF output resistance
DAC gain factor
1.30
1.35 1.40
V
7K
11K
15K
W
See
Table 4
Imbalance between DACs, (KIMBAL)
See Note 6
Imbalance between positive and negative sync,
(KIMBAL(SYNC))
See Note 6
VO(DAC) DAC output compliance voltage (sync+video)
RL = 37.5 Ω, See Note 7
RL = 75 Ω, See Note 7
AGY
24
Internal reference
GBR sync-on-green and YPbPr sync-on-Y/sync-
ABPb and ARPr
17.3
on-all
AGY
24.9
External reference
ABPb and ARPr
17.5
I(FS)
GBR sync-on-all
AGY
24
Internal reference
ABPb and ARPr
24
AGY
24.9
External reference
ABPb and ARPr
24.9
ro
CO
tr(DAC)
tf(DAC)
td(A)
DAC output resistance
DAC output capacitance (pin capacitance)
DAC output current rise time
DAC output current fall time
Analog output delay
See Note 10
57
10% to 90% of full scale
10% to 90% of full scale
Measured from CLK=VIH(min) to 50% of full-scale
transition, See Note 8
±5%
±2%
1
1.2
V
2
2.4
26.67
28
18.67 19.7
mA
26.67 27.2
18.67 19.3
26.67
28
26.67
28
mA
26.67 27.2
26.67 27.2
92 kΩ
8
pF
2
ns
2
ns
9 ns
tS
Analog output settling time
Measured from 50% of full scale transition on
output to output settling, within 2%, See Note 9
5
9 ns
SNR
Signal -to-noise ratio
1 MHz, –1 dBFS digital sine input, measured from
0 MHz to 8.8 MHz
57.5
dB
SFDR
Spurious-free dynamic range
1MHz, –1 dBFS digital sine input, measured from
0 MHz to 8.8 MHz
64
dB
BW(1 dB) Bandwidth
See Note 11
40
MHz
NOTES:
4. PSRR is measured with a 0.1 µF capacitor between the COMP and AVDD terminal; with a 0.1 µF capacitor connected between the VREF terminal and
AVSS. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a double-terminated 75 Ω (=37.5 Ω)
load. PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
5. Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limits from characterization only.
6. The imbalance between DACs applies to all possible pairs of the three DACs. KIMBAL is assured over full temperature range. In parts labeled
THS8133CPHP,KIMBAL(SYNC)isassuredat25°C.InpartslabeledTHS8133ACPHP,KIMBAL(SYNC)andTHS8133BCPHP,KIMBAL(SYNC)areassured
over the full temperature range.
7. Nominal values at R(FS) = R(FSnom) : Maximum values at R(FS) = R(FSnom) ÷ 1.2. Maximum limits from characterization only.
8. This value excludes the digital process delay, td(D). Limit from characterization only.
9. Maximum limit from characterization only
10. Limit from characterization only
11. This bandwidth relates to the output amplitude variation in excess of the droop from the sinx/x sampled system. Since the output is a sample-and-hold
signal, a sin(π × Fin ÷ Fclk) ÷ (π × Fin ÷ Fclk) roll-off is observed, which accounts e.g. at Fin = 40 MHz and Fclk = 80 MSPS for –3.92 dB signal drop (sync
droop). The total DAC output variation (device droop) consists of this and an additional amount (excess droop) caused by the output impedance of the
device, as shown in Table 5.
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