TMS320C6678 Datasheet, PDF (64/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010
Table 3-2
Device State Control Registers (Part 3 of 3)
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Address Start
0x026202A0
0x026202BC
0x026202C0
0x02620300
0x02620304
0x02620308
0x0262030C
0x02620310
0x02620314
0x02620318
0x0262031C
0x02620320
0x02620324
0x02620328
0x0262032C
0x02620330
0x02620334
0x02620338
0x0262033C
End of Table 3-2
Address End
0x026202BB
0x026202BF
0x026202FF
0x02620303
0x02620307
0x0262030B
0x0262030F
0x02620313
0x02620317
0x0262031B
0x0262031F
0x02620323
0x02620327
0x0262032B
0x0262032F
0x02620333
0x02620337
0x0262033B
0x0262033F
Size Acronym
28B Reserved
4B IPCARH
64B Reserved
4B TINPSEL
4B TOUTPSEL
4B RSTMUX0
4B RSTMUX1
4B RSTMUX2
4B RSTMUX3
4B RSTMUX4
4B RSTMUX5
4B RSTMUX6
4B RSTMUX7
4B MAINPLLCTL0
4B Reserved
4B DDR3PLLCTL0
4B Reserved
4B PAPLLCTL0
4B Reserved
Description
See section 3.3.15
See section 3.3.16
See section 3.3.17
See section 3.3.18
See section 7.8 ‘‘Main PLL and PLL Controller’’ on page 215
See section 7.9 ‘‘DD3 PLL’’ on page 228
See section 7.10 ‘‘PASS PLL’’ on page 230
3.3.1 Device Status Register
The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until a power-on reset. The Device Status Register is shown in
Figure 3-1 and described in Table 3-3.
Figure 3-1 Device Status Register
31
18
17
16
15
14
13
1
0
Reserved
R-0
PACLKSEL
PCIESSEN
R-x
PCIESSMODE[1:0
R/W-xx
BOOTMODE[12:0]
R/W-xxxxxxxxxxxx
LENDIAN
R-x ⁽¹⁾
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
Table 3-3
Device Status Register Field Descriptions (Part 1 of 2)
Bit Field
31-18 Reserved
17 PACLKSEL
16 PCIESSEN
Description
Reserved. Read only, writes have no effect.
PA Clock select to select the reference clock for PA Sub-System PLL
0 = Selects PASSCLKP/N
1 = Selects output of Main PLL MUX (SYSCLK vs. ALTCORECLK - depending on CORECLKSEL pin)
PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
64 Device Configuration
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