TMS320C6678 Datasheet, PDF (112/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010
7.4 Enhanced Direct Memory Access (EDMA3) Controller
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The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the C6678 DSP, TPCC0, TPCC1, and TPCC2. TPCC0 is optimized to
be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are to be used for the remaining
traffic.
Each EDMA3 Channel Controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
› Array (multiple bytes)
› Frame (multiple arrays)
› Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 128 PaRAM entries for TPCC0, 512 each for TPCC1 and TPCC2
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• 2 transfer controllers and 2 event queues with programmable system-level priority for TPCC0, 4 transfer
controllers and 4 event queues with programmable system-level priority per channel controller for TPCC1 and
TPCC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
In the context of this document, TPTCs associated with TPCC0 are referred to as TPCC0 TPTC0 and1. TPTCs
associated with TPCC1 and 2 are each referred to as TPCCx TPTC0 - 3, where x is 1 or 2. Each of the transfer
controllers has a direct connection to the switched central resource (SCR). ‘‘DSP/2 Data SCR Connection Matrix’’
on page 82 and ‘‘DSP/3 Data SCR Connection Matrix’’ on page 82 lists the peripherals that can be accessed by the
transfer controllers.
112 TMS320C6678 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated