TMS320C6678 Datasheet, PDF (239/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS691—November 2010
Table 7-84 SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-45 and Figure 7-46)
No.
6 toh(SPC-SIMO)
6 toh(SPC-SIMO)
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
20 td(SPC-SCS)
20 td(SPC-SCS)
20 td(SPC-SCS)
20 td(SPC-SCS)
tw(SCSH)
End of Table 7-84
Parameter
Min
Max
Unit
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for 0.5*tc - 2
ns
final bit. Polarity = 1 Phase = 0
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for 0.5*tc - 2
ns
final bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0
2*P2 - 5
2*P2 + 5
ns
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0
2*P2 - 5
2*P2 + 5
ns
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0 1*P2 - 5
1*P2 + 5
ns
Phase = 0
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0 0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
Phase = 1
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1 1*P2 - 5
1*P2 + 5
ns
Phase = 0
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1 0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
Phase = 1
Minimum inactive time on SPIx_SCS\ pin between two transfers when
2*P2 - 5
ns
SPIx_SCS\ is not held using the CSHOLD feature.
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TMS320C6678 Peripheral Information and Electrical Specifications 239