TMS320C6678 Datasheet, PDF (241/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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7.14 HyperLink Peripheral
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010
The TMS320C6678 will include the HyperLink bus for companion chip/die interfaces. This is a four lane SerDes
interface designed to operate at 12.5 Gbps per lane from pin-to-pin and at 18 Gbps per lane from die-to-die. The
interface is used to connect with external accelerators. The HyperLink links must be connected with DC coupling.
The interface includes the Serial Station Management Interfaces used to send power management and flow messages
between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output
buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.
Table 7-85 HyperLink Peripheral Timing Requirements
See Figure 7-47,Figure 7-48,Figure 7-49
No.
Parameter
FL Interface
1 tc(MCMTXFLCLK)
Clock Period - MCMTXFLCLK (C1)
2 tw(MCMTXFLCLKH)
High Pulse Width - MCMTXFLCLK
3 tw(MCMTXFLCLKL)
Low Pulse Width - MCMTXFLCLK
6 tsu(MCMTXFLDAT-MCMTXFLCLKH) Setup Time - MCMTXFLDAT valid before MCMTXFLCLK high
7 th(MCMTXFLCLKH-MCMTXFLDAT) Hold Time - MCMTXFLDAT valid after MCMTXFLCLK high
6 tsu(MCMTXFLDAT-MCMTXFLCLKL) Setup Time - MCMTXFLDAT valid before MCMTXFLCLK low
7 th(MCMTXFLCLKL-MCMTXFLDAT) Hold Time - MCMTXFLDAT valid after MCMTXFLCLK low
PM Interface
1 tc(MCMRXPMCLK)
Clock Period - MCMRXPMCLK (C3)
2 tw(MCMRXPMCLK)
High Pulse Width - MCMRXPMCLK
3 tw(MCMRXPMCLK)
Low Pulse Width - MCMRXPMCLK
6 tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup Time - MCMRXPMDAT valid before MCMRXPMCLK high
7 th(MCMRXPMCLKH-MCMRXPMDAT) Hold Time - MCMRXPMDAT valid after MCMRXPMCLK high
6 tsu(MCMRXPMDAT-MCMRXPMCLKL) Setup Time - MCMRXPMDAT valid before MCMRXPMCLK low
7 th(MCMRXPMCLKL-MCMRXPMDAT) Hold Time - MCMRXPMDAT valid after MCMRXPMCLK low
End of Table 7-85
Min Max Unit
6
ns
0.4*C1 0.6*C1 ns
0.4*C1 0.6*C1 ns
1
ns
1
ns
1
ns
1
ns
6
ns
0.4*C3 0.6*C3 ns
0.4*C3 0.6*C3 ns
1
ns
1
ns
1
ns
1
ns
Table 7-86 HyperLink Peripheral Switching Characteristics (Part 1 of 2)
See Figure 7-47,Figure 7-48,Figure 7-49
No.
Parameter
FL Interface
1 tc(MCMRXFLCLK)
Clock Period - MCMRXFLCLK (C2)
2 tw(MCMRXFLCLKH)
High Pulse Width - MCMRXFLCLK
3 tw(MCMRXFLCLKL)
Low Pulse Width - MCMRXFLCLK
4 tosu(MCMRXFLDAT-MCMRXFLCLKH) Setup Time - MCMRXFLDAT valid before MCMRXFLCLK high
5 toh(MCMRXFLCLKH-MCMRXFLDAT) Hold Time - MCMRXFLDAT valid after MCMRXFLCLK high
4 tosu(MCMRXFLDAT-MCMRXFLCLKL) Setup Time - MCMRXFLDAT valid before MCMRXFLCLK low
5 toh(MCMRXFLCLKL-MCMRXFLDAT) Hold Time - MCMRXFLDAT valid after MCMRXFLCLK low
PM Interface
1 tc(MCMTXPMCLK)
Clock Period - MCMTXPMCLK (C4)
2 tw(MCMTXPMCLK)
High Pulse Width - MCMTXPMCLK
3 tw(MCMTXPMCLK)
Low Pulse Width - MCMTXPMCLK
4 tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup Time - MCMTXPMDAT valid before MCMTXPMCLK high
5 toh(MCMTXPMCLKH-MCMTXPMDAT) Hold Time - MCMTXPMDAT valid after MCMTXPMCLK high
Min Max Unit
6
ns
0.4*C2 0.6*C2 ns
0.4*C2 0.6*C2 ns
1.1
ns
1.1
ns
1.1
ns
1.1
ns
6
ns
0.4*C4 0.6*C4 ns
0.4*C4 0.6*C4 ns
1.1
ns
1.1
ns
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TMS320C6678 Peripheral Information and Electrical Specifications 241