TMS320C6678 Datasheet, PDF (231/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS691—November 2010
7.10.2 PASS PLL Device-Specific Information
As shown in Figure 7-39, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Packet
Accelerator Sub-System. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks
of the PASS PLL are affected as described in Section 7.7 ‘‘Reset Controller’’ on page 208. PASS PLL is unlocked only
during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during
any of the other resets.
Table 7-79 PASS PLL Timing Requirements
(See Figure 7-41 and Figure 7-35)
No.
1 tc(PASSCLKN)
Parameter
PASSCLK[P:N]
Cycle Time _ PASSCLKN cycle time
1 tc(PASSCLKP)
Cycle Time _ PASSCLKP cycle time
3 tw(PASSCLKN)
Pulse Width _ PASSCLKN high
2 tw(PASSCLKN)
Pulse Width _ PASSCLKN low
2 tw(PASSCLKP)
Pulse Width _ PASSCLKP high
3 tw(PASSCLKP)
Pulse Width _ PASSCLKP low
4 tr(PASSCLKN_250mv) Transition Time _ PASSCLKN Rise time (250mV)
4 tf(PASSCLKN_250mv) Transition Time _ PASSCLKN Fall time (250mV)
4 tr(PASSCLKP_250mv) Transition Time _ PASSCLKP Rise time (250mV)
4 tf(PASSCLKP_250mv) Transition Time _ PASSCLKP Fall time (250mV)
5 tj(PASSCLKN)
Jitter, Peak_to_Peak _ Periodic PASSCLKN
5 tj(PASSCLKP)
Jitter, Peak_to_Peak _ Periodic PASSCLKP
Min
Max Unit
3.2
3.2
0.45*tc(PASSCLKN)
0.45*tc(PASSCLKN)
0.45*tc(PASSCLKP)
0.45*tc(PASSCLKP)
50
50
50
50
6.4
6.4
0.55*tc(PASSCLKN)
0.55*tc(PASSCLKN)
0.55*tc(PASSCLKP)
0.55*tc(PASSCLKP)
350
350
350
350
100
100
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps, pk-pk
ps, pk-pk
Figure 7-41 PASS PLL Timing
<CLK_NAME>CLKN
<CLK_NAME>CLKP
1
2
3
4
5
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TMS320C6678 Peripheral Information and Electrical Specifications 231