TMS320C6678 Datasheet, PDF (252/259 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010
Figure 7-60 Trace Timing
A
T_PLH
B
T_PHL
1
2
3
C
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7.27.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.27.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6678 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
7.27.3.2 JTAG Electrical Data/Timing
Table 7-98 JTAG Test Port Timing Requirements
(see Figure 7-61)
No.
1 t_c(TCK)
1a tw(TCKH)
1b tw(TCKL)
3 tsu(TDI-TCK)
3 tsu(TMS-TCK)
4 th(TCK-TDI)
4 th(TCK-TMS)
End of Table 7-98
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
input setup time, TDI valid to TCK high
input setup time, TMS valid to TCK high
input hold time, TDI valid from TCK high
input hold time, TMS valid from TCK high
Min
Max Unit
20
ns
8
ns
8
ns
2
ns
2
ns
10
ns
10
ns
Table 7-99 JTAG Test Port Switching Characteristics ⁽¹⁾
(see Figure 7-61)
No.
2 t_d(TCKL-TDOV)
End of Table 7-99
Parameter
Delay time, TCK low to TDO valid
1 Over recommended operating conditions.
Min
Max Unit
8 ns
252 TMS320C6678 Peripheral Information and Electrical Specifications
Copyright 2010 Texas Instruments Incorporated