TLC3574IDW Datasheet, PDF (6/49 Pages) Texas Instruments – 5-V ANALOG,3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 10-V INPUTS

TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
general electrical characteristics over recommended operating free-air temperature range, single-
ended input, normal long sampling, 200 KSPS, AV_DD = 5 V, V_REFP = 4 V, V_REFM = 0 V,
SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source
resistance = 25 Ω (unless otherwise noted)
TLC3574/78 and TLC2574/78
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
Resolution
14
bits
Analog Input
Voltage range
−10
10 V
Selected analog input channel bias current
Selected channel at 10 V
Selected channel at –10 V
0.8
−1.6 −1.2
1.6
mA
Impedance
10
kΩ
Capacitance
30
pF
Reference
VREFP
VREFM
Positive reference voltage
Negative reference voltage
Input impedance
No conversion (AVDD = 5V, CS= DVDD,
SCLK=DGND)
Normal long sampling (AVDD = 5V, CS=DGND,
SCLK = 25 MHz, External conversion clock)
3.96
4 4.04 V
0 AGND
V
100
MΩ
8.3 12.5
kΩ
Reference current
Internal oscillation frequency
t(conv) Conversion time
No conversion (AVDD = 5 V,
SCLK = DGND, CS = DVDD)
Normal long sampling (AVDD = 5 V, CS = DGND,
External conversion clock, SCLK = 25 MHz,
VREF = 5 V)
DVDD = 2.7 V – 5.5 V
Internal OSC, 6.5 MHz minimum
TLC3574/78
TLC2574/78
Conversion clock is external source,
SCLK = 25 MHz (see Note 1)
TLC3574/78
TLC2574/78
1.5 µA
0.4 0.6 mA
6.5
MHz
2.785
2.015
µS
2.895
2.095
Acquisition time
Normal short sampling
1.2
µS
Throughput rate (see Note 2)
Normal long sampling, fixed channel
in mode 00 or 01
200
KSPS
† _{All typical values are at TA = 25°C.}
NOTES: 1. Conversion time t(conv) is (18 × 4 × SCLK) + 15 ns for TLC3574/78. Conversion time is (13 × 4 × SCLK) + 15 ns for TLC2574/78.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
6
WWW.TI.COM