TLC3574IDW Datasheet, PDF (15/49 Pages) Texas Instruments – 5-V ANALOG,3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 10-V INPUTS

TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
timing requirements over recommended operating free-air temperature range, AV_DD = 5 V,
DV_DD = 5 V, V_REFP = 4 V, V_REFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
FS trigger
PARAMETERS
td(8)
tsu(3)
tw(3)
td(9)
Delay time, delay from CS falling edge to FS rising edge at 25-pF load
Setup time, FS rising edge before SCLK falling edge at 25-pF load
Pulse width of FS high, at 25-pF load
Delay time, delay from FS rising edge to MSB of SDO valid
(reaches 90% final level), at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
td(10) Delay time, delay from FS rising edge to next FS rising edge, at 25-pF load
td(11)
Delay time, delay from FS rising edge to INT rising edge, at
10-pF load
† _{Specified by design}
DVDD = 5 V
DVDD = 2.7 V
MIN
0.5
0.25×tc(1)
0.75×tc(1)
Required
sampling time +
conversion time
0
0
TYP
MAX
tc(1)
0.5×tc(1)+ 5
1.25×tc(1)
26
30†
UNIT
tc(1)
ns
ns
ns
ns
6
ns
16†
td(10)
VIH
CS
VIL
td(8)
tw(3)
FS
SCLK
tsu(3)
1
16
SDI
Don’t Care
ID15 ID1
ID0
Don’t Care
ID15
Don’t Care
td(9)
SDO
Hi-Z
OD15
OD1 OD0
Hi-Z
EOC
OR
INT
VOH
VOH
OD15
Don’t Care
td(11)
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 3. Critical Timing for FS Trigger
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