TLC3574IDW Datasheet, PDF (2/49 Pages) Texas Instruments – 5-V ANALOG,3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 10-V INPUTS

TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
description (continued)
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog
multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin,
CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK
operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are
designed to operate with low-power consumption. The power saving feature is further enhanced with
autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in.
The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78
and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.
TA
−40°C to 85°C
20-TSSOP
(PW)
TLC2574IPW
TLC3574IPW
AVAILABLE OPTIONS
PACKAGED DEVICES
20-SOIC
(DW)
20-PDIP
(N)
24-SOIC
(DW)
TLC2574IDW TLC2574IN
TLC2578IDW
TLC3574IDW TLC3574IN
TLC3578IDW
24-TSSOP
(PW)
TLC2578IPW
TLC3578IPW
functional block diagram
DVDD AVDD
REFP
COMP
REFM
X8^† X4^‡
A0 A0
A1 A1
A2 A2
A3 A3
A4 X
A5 X
A6 X
A7 X
SDI
SCLK
CS
FS
CSTART
Signal
Scaling
Analog
MUX
OSC
Command
Decode
CMR (4 MSBs)
SAR
ADC
Conversion
Clock
CFR
4-Bit
Counter
Control
Logic
FIFO
X8
SDO
EOC/INT
DGND AGND
† _{TLC3578, TLC2578}
‡ _{TLC3574, TLC2574}
NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated in by CS falling edge if CS initiates the conversion operation cycle, or gated
in by the rising edge of FS if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high.
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