TLC2543-Q1 Datasheet, PDF (6/24 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543ĆQ1
ą
12ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS218B − NOVEMBER 2003 − REVISED NOVEMBER 2004
operating characteristics over recommended operating free-air temperature range,
V_CC = V_ref+ = 4.5 V to 5.5 V, f_{(I/O CLOCK)} = 4.1 MHz
PARAMETER
TEST CONDITIONS MIN TYP†
MAX
UNIT
EL
Linearity error (see Note 5)
ED
Differential linearity error
EO
Offset error (see Note 6)
See Figure 2
See Figure 2
See Note 2 and
Figure 2
±1
LSB
±1
LSB
± 1.5
LSB
EG
Gain error (see Note 6)
See Note 2 and
Figure 2
±1
LSB
ET
Total unadjusted error (see Note 7)
DATA INPUT = 1011
± 1.75
LSB
2048
Self-test output code (see Table 3 and Note 8)
DATA INPUT = 1100
DATA INPUT = 1101
0
4095
t(conv)
Conversion time
See Figure 9 −
Figure 14
8
10
µs
See Figure 9 −
tc
Total cycle time (access, sample, and conversion)
Figure 14 and Note 9
10 + total
I/O CLOCK
periods +
µs
td(I/O-EOC)
tacq
Channel acquisition time (sample)
See Figures 9 −14
and Note 9
4
I/O
12 CLOCK
periods
tv
Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6
10
ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 6
150
ns
td(I/O-EOC) Delay time, last I/O CLOCK↓ to EOC↓
See Figure 7
1.5
2.2
µs
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB / LSB)
See Figure 8
100
ns
tPZH, tPZL
Enable time, CS↓ to DATA OUT (MSB / LSB driven)
See Figure 3
0.7
1.3
µs
tPHZ, tPLZ
Disable time, CS↑ to DATA OUT (high impedance)
See Figure 3
70
150
ns
tr(EOC)
Rise time, EOC
See Figure 8
15
50
ns
tf(EOC)
Fall time, EOC
See Figure 7
15
50
ns
tr(bus)
Rise time, data bus
See Figure 6
15
50
ns
tf(bus)
Fall time, data bus
See Figure 6
15
50
ns
td(I/O-CS)
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
5
µs
† _{All typical values are at TA = 25°C.}
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that
applied to REF − convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether
the conversion is aborted or the conversion results are valid.
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