TLC2543-Q1 Datasheet, PDF (13/24 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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TLC2543ĆQ1
12ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS218B − NOVEMBER 2003 − REVISED NOVEMBER 2004
PRINCIPLES OF OPERATION
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random and the first conversion result
should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O
cycle. The first conversion after the device has returned from the power-down state may not read accurately
due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT.
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N −1) conversion cycle The conversion cycle just prior to the current I/O cycle.
Next (N + 1) I/O cycle
The I/O period that follows the current conversion cycle.
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion is begun
immediately after the twelfth falling edge of the current I/O cycle.
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