TLC2543-Q1 Datasheet, PDF(19/24 Page) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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TLC2543-Q1 Datasheet, PDF (19/24 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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TLC2543ÄQ1

12ÄBIT ANALOGÄTOÄDIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SGLS218B â NOVEMBER 2003 â REVISED NOVEMBER 2004

PRINCIPLES OF OPERATION

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF â)

voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and

the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks

at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF â. When the voltage at the

summing node is greater than the trip point of the threshold detector (approximately 1/2 VCC ), a bit 0 is placed

in the output register and the 4096-weight capacitor is switched to REFâ. When the voltage at the summing node

is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor

remains connected to REF+ through the remainder of the successive-approximation process. The process is

repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are

determined. With each step of the successive-approximation process, the initial charge is redistributed among

the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

reference voltage inputs

The two reference inputs used with the device are the voltages applied to the REF+ and REFâ terminals. These

voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale

reading respectively. These voltages and the analog input should not exceed the positive supply or be lower

than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the

input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower

than REFâ terminal voltage.

Threshold

Detector

4096

2048

1024

Node 4096

REF+

To Output

Latches

REF â

Figure 15. Simplified Model of the Successive-Approximation System

â¢ POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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