BQ4832Y Datasheet, PDF (6/18 Pages) Texas Instruments – RTC Module With 32Kx8 NVSRAM

bq4832Y
The second approach uses a bq4832Y test mode. When
the frequency test mode enable bit FTE in the days reg-
ister is set to a 1, and the oscillator is running at exactly
32,768 Hz, the LSB of the seconds register toggles at 512
Hz. Any deviation from 512 Hz indicates the degree and
direction of oscillator frequency shift at the test tem-
perature. For example, a reading of 512.01024 Hz indi-
cates a (1E6*0.01024)/512 or +20 ppm oscillator fre-
quency error, requiring ten steps of negative calibration
(10*-2.034 or -20.34) or 001010 to be loaded into the cali-
bration byte for correction. To read the test frequency,
the bq4832Y must be selected and held in an extended
read of the seconds register, location 7FF9, without hav-
ing the read bit set. The frequency appears on DQ0.
The FTE bit must be set using the write bit control. The
FTE bit must be reset to 0 for normal clock operation to
resume.
Power-On Reset
The bq4832Y provides a power-on reset, which pulls the
RST pin low on power-down and remains low on power-
up for tCER after VCC passes VPFD.
Watchdog Timer
The watchdog circuit monitors the microprocessor’s ac-
tivity. If the processor does not reset the watchdog timer
within the programmed time-out period, the circuit as-
serts the INT or RST pin. The watchdog timer is acti-
vated by writing the desired time-out period into the
eight-bit watchdog register described in Table 3 (device
address 7FF7). The five bits (BM4–BM0) store a binary
multiplier, and the two lower-order bits (WD1–WD0) se-
lect
the
resolution,
where
00
=
1
16
second,
01
=
1
4
second,
10 = 1 second, and 11 = 4 seconds.
The time-out period is the multiplication of the five-bit
multiplier with the two-bit resolution. For example,
writing 00011 in BM4–BM0 and 10 in WD1–WD0 re-
sults in a total time-out setting of 3 x 1 or 3 seconds. A
multiplier of zero disables the watchdog circuit. Bit 7 of
the watchdog register (WDS) is the watchdog steering
bit. When WDS is set to a 1 and a time-out occurs, the
watchdog asserts a reset pulse for tCER on the RST pin.
During the reset pulse, the watchdog register is cleared
to all zeros disabling the watchdog. When WDS is set to
a 0, the watchdog asserts the INT pin on a time-out.
The INT pin remains low until the watchdog is reset by
the microprocessor or a power failure occurs. Addition-
ally, when the watchdog times out, the watchdog flag bit
(WDF) in the flags register, location 7FF0, is set.
To reset the watchdog timer, the microprocessor must
write to the watchdog register. After being reset by a
write, the watchdog time-out period starts over. As a
precaution, the watchdog circuit is disabled on a power
failure. The user must, therefore, set the watchdog at
boot-up for activation.
Interrupts
The bq4832Y allows four individually selected interrupt
events to generate an interrupt request on the INT pin.
These four interrupt events are:
n The watchdog timer interrupt, programmable to
occur according to the time-out period and conditions
described in the watchdog timer section.
n The periodic interrupt, programmable to occur once
every 122µs to 500ms.
n The alarm interrupt, programmable to occur once per
second to once per month.
n The power-fail interrupt, which can be enabled to be
asserted when the bq4832Y detects a power failure.
The periodic, alarm, and power-fail interrupts are en-
abled by an individual interrupt-enable bit in register
7FF6, the interrupts register. When an event occurs, its
event flag bit in the flags register, location 7FF0, is set.
If the corresponding event enable bit is also set, then an
interrupt request is generated. Reading the flags regis-
ter clears all flag bits and makes INT high impedance.
To reset the flag register, the bq4832Y addresses must
be held stable at location 7FF0 for at least 50ns to avoid
inadvertent resets.
Periodic Interrupt
Bits RS3–RS0 in the interrupts register program the
rate for the periodic interrupt. The user can interpret
the interrupt in two ways: either by polling the flags
register for PF assertion or by setting PIE so that INT
goes active when the bq4832Y sets the periodic flag.
Reading the flags register resets the PF bit and re-
turns INT to the high-impedance state. Table 4 shows
the periodic rates.
MSB
7
WDS
6
BM4
Table 3. Watchdog Register Bits
Bits
5
4
3
2
BM3
BM2
BM1
BM0
1
WD1
LSB
0
WD0
Sept. 1996 C
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