BQ4832Y Datasheet, PDF (3/18 Pages) Texas Instruments – RTC Module With 32Kx8 NVSRAM

bq4832Y
Address Map
The bq4832Y provides 16 bytes of clock and control
status registers and 32,752 bytes of storage RAM.
Figure 2 illustrates the address map for the bq4832Y.
Table 1 is a map of the bq4832Y registers, and Table 2
describes the register bits.
Memory Interface
Read Mode
The bq4832Y is in read mode whenever OE (output en-
able) is low and CE (chip enable) is low. The device ar-
chitecture allows ripple-through access of data from
eight of 262,144 locations in the static storage array.
Thus, the unique address specified by the 15 address in-
puts defines which one of the 32,768 bytes of data is to
be accessed. Valid data is available at the data I/O pins
within tAA (address access time) after the last address
input signal is stable, providing that the CE and OE
(output enable) access times are also satisfied. If the CE
and OE access times are not met, valid data is available
after the latter of chip enable access time (tACE) or out-
put enable access time (tOE).
CE and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the
address inputs are changed while CE and OE remain low,
output data remains valid for tOH (output data hold time),
but goes indeterminate until the next address access.
Write Mode
The bq4832Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the
latter-occurring falling edge of WE or CE. A write is ter-
minated by the earlier rising edge of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return high for a minimum of tWR2 from CE
or tWR1 from WE prior to the initiation of another read
or write cycle.
Data-in must be valid tDW prior to the end of write and
remain valid for tDH1 or tDH2 afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CE and OE, a low on WE disables the outputs tWZ after
WE falls.
16 Bytes
Clock and ^7FFF
Control Status _7FF0
Registers
7FEF
32,752
Bytes
Storage
RAM
0000
0
Year
7FFF
1
Month
7FFE
2
Date
7FFD
3
Days
7FFC
4
Hours
7FFB
5
Minutes
7FFA
6
Seconds 7FF9
7
Control
7FF8
8 Watchdog 7FF7
9 Interrupts 7FF6
10 Alarm Date 7FF5
11 Alarm Hours 7FF4
12 Alarm Minutes 7FF3
13 Alarm Seconds 7FF2
Tenths/
14 _Hundredths 7FF1
15
Flags
7FF0
Sept. 1996 C
Figure 2. Address Map
FG483201.eps
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