BQ4832Y Datasheet, PDF (14/18 Pages) Texas Instruments – RTC Module With 32Kx8 NVSRAM

bq4832Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
tPF
VCC slew, 4.50 to 4.20 V
tFS
VCC slew, 4.20 to VSO
tPU
VCC slew, VSO to VPFD
(max.)
Minimum
300
10
0
Typical
-
-
-
tCER
Chip enable recovery time
40
100
tDR
tWPT
Data-retention time in
absence of V_CC
Write-protect time
10
-
40
100
Maximum Unit
-
µs
-
µs
Conditions
-
µs
Time during which SRAM is
200
ms write-protected after VCC
passes VFPD on power-up.
-
years TA = 25°C. (2)
Delay after VCC slews down
160
µs past VPFD before SRAM is
write-protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Notes:
1. PWRIE is set to “1” to enable power fail interrupt.
2. RST and INT are open drain and require an external pull-up resistor.
14
Sept. 1996 C