BQ4832Y Datasheet, PDF (4/18 Pages) Texas Instruments – RTC Module With 32Kx8 NVSRAM

bq4832Y
Data-Retention Mode
With valid VCC applied, the bq4832Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself tWPT after VCC falls below VPFD.
All outputs become high impedance, and all inputs are
treated as “don’t care.”
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory
cycle fails to terminate within time tWPT, write-
protection takes place. When VCC drops below VSO, the
control circuit switches power to the internal energy
source, which preserves data.
The internal coin cell maintains data in the bq4832Y af-
ter the initial application of VCC for an accumulated pe-
riod of at least 10 years when VCC is less than VSO. As
system power returns and Vcc rises above VSO, the bat-
tery is disconnected, and the power supply is switched to
external VCC. Write-protection continues for tCER after
VCC reaches VPFD to allow for processor stabilization.
After tCER, normal RAM operation can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4832Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4832Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because the
internal counters are not halted by setting the read bit,
reading the clock locations has no effect on clock accu-
racy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
Table 1. bq4832Y Clock and Control Register Map
Address
7FFF
7FFE
7FFD
7FFC
7FFB
7FFA
7FF9
7FF8
7FF7
7FF6
7FF5
7FF4
7FF3
7FF2
7FF1
7FF0
D7
X
X
X
X
X
OSC
W
WDS
AIE
ALM3
ALM2
ALM1
ALM0
WDF
D6
D5
D4
10 Years
X
X 10 Month
X
10 Date
FTE
X
X
X
10 Hours
10 Minutes
10 Seconds
R
S
BM4 BM3 BM2
PWRIE ABE PIE
X
10-date alarm
X
10-hour alarm
Alarm 10 minutes
Alarm 10 seconds
0.1 seconds
AF PWRF BLF
D3
D2
D1
Year
Month
Date
X
Day
Hours
Minutes
Seconds
Calibration
BM1 BM0 WD1
RS3 RS2 RS1
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.01 seconds
PF
X
X
D0
WD0
RS0
X
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
BLF = 1 for low battery.
OSC = 1 stops the clock oscillator.
Interrupt enables are cleared on power-up.
Range (h)
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–31
01–31
00–23
00–59
00–59
00–99
Register
Year
Month
Date
Days
Hours
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.1/0.01 seconds
Flags
Sept. 1996 C
4