BQ4832Y Datasheet, PDF (5/18 Pages) Texas Instruments – RTC Module With 32Kx8 NVSRAM

bq4832Y
Table 2. Clock and Control Register Bits
Bits
ABE
AF
AIE
ALM0–ALM3
BLF
BM0–BM4
FTE
OSC
PF
PIE
PWRF
PWRIE
R
RS0–RS3
S
W
WD0–WD1
WDF
WDS
Description
Alarm interrupt enable in
battery-backup mode
Alarm interrupt flag
Alarm interrupt enable
Alarm repeat rate
Battery-low flag
Watchdog multiplier
Frequency test mode enable
Oscillator stop
Periodic interrupt flag
Periodic interrupt enable
Power-fail interrupt flag
Power-fail interrupt enable
Read clock enable
Periodic interrupt rate
Calibration sign
Write clock enable
Watchdog resolution
Watchdog flag
Watchdog steering
Setting the Clock
Bit D7 of the control register is the write bit. Like
the read bit, the write bit when set to a 1 halts up-
dates to the clock/calendar memory locations. Once
frozen, the locations can be written with the desired
information in 24-hour BCD format. Resetting the
write bit to 0 causes the written values to be trans-
ferred to the internal clock counters and allows up-
dates to the user-accessible registers to resume
within one second. Use the write bit, D7, only when
updating the time registers (7FFF-7FF9).
Calibrating the Clock
The bq4832Y real-time clock is driven by a quartz con-
trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4832Y
package along with the battery. The clock accuracy of
the bq4832Y module is tested to be within 20ppm or
about 1 minute per month at 25°C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4832Y of-
fers onboard software clock calibration. The user can
adjust the calibration based on the typical operating
temperature of individual applications.
The software calibration bits are located in the control
register. Bits D0–D4 control the magnitude of correc-
tion, and bit D5 the direction (positive or negative) of
correction. Assuming that the oscillator is running at
exactly 32,786 Hz, each calibration step of D0–D4 ad-
justs the clock rate by +4.068 ppm (+10.7 seconds per
month) or -2.034 ppm (-5.35 seconds per month) depend-
ing on the value of the sign bit D5. When the sign bit is
1, positive adjustment occurs; a 0 activates negative ad-
justment. The total range of clock calibration is +5.5 or
-2.75 minutes per month.
Two methods can be used to ascertain how much cali-
bration a given bq4832Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system’s environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock
on or off. If the bq4832Y is to spend a significant pe-
riod of time in storage, the clock oscillator can be
turned off to preserve battery capacity. OSC set to 1
stops the clock oscillator. When OSC is reset to 0,
the clock oscillator is turned on and clock updates to
user-accessible memory locations occur within one
second.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
Figure 3. Frequency Error
Sept. 1996 C
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