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BQ24070 Datasheet, PDF (6/26 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC
bq24070
SLUS694A – MARCH 2006 – REVISED MARCH 2006
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TIMERS
K(TMR)
R(TMR) (9)
t(PRECHG)
I(FAULT)
Timer set factor
External resistor limits
Precharge timer
Timer fault recovery pullup from
OUT to BAT
t(CHG) = K(TMR) × R(TMR)
0.313
0.360
0.414
s/Ω
30
100
kΩ
0.09 × t(CHG) 0.10 × t(CHG) 0.11 × t(CHG)
s
1
kΩ
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)
V(SLPENT) (10)
V(SLPEXIT) (10)
Sleep-mode entry threshold
Sleep-mode exit threshold
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
V(UVLO)≤ VI(BAT)≤ VO(BAT-REG),
No t(BOOT-UP) delay
VVCC ≥
VI(BAT)
+190 mV
VVCC ≤
VI(BAT)
+125 mV
V
t(DEGL)
Deglitch time for sleep mode(11)
R(TMR) = 50 kΩ,
V(IN) decreasing below threshold, 100-ns
fall time, 10-mv overdrive
22.5
ms
START-UP CONTROL BOOT-UP
t(BOOT-UP)
Boot-up time
On the first application of input with
Mode Low
120
150
180
ms
SWITCHING POWER SOURCE TIMING
tSW-BAT
Switching power source from input
to battery
THERMAL SHUTDOWN REGULATION(12)
When input applied. Measure from:
[PG: Lo → Hi to I(IN) > 5 mA],
I(OUT) = 100 mA,
RTRM = 50 K
50
µs
T(SHTDWN)
TJ(REG)
UVLO
Temperature trip
Thermal hysteresis
Temperature regulation limit
TJ (Q1 and Q3 only)
TJ (Q1 and Q3 only)
TJ (Q2)
155
30
°C
115
135
V(UVLO)
Undervoltage lockout
Hysteresis
Decreasing VCC
2.45
2.50
2.65
V
27
mV
(9) To disable the safety timer and charge termination, tie TMR to the VREF pin.
(10) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).
(11) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
(12) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
6
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